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Preliminary
Features
* Operating voltage: 2.4V~5.0V * Up to 1ms (0.5ms) instruction cycle with 4MHz (8MHz) * Watchdog Timer * Low voltage reset * 4-level subroutine nesting
HT83XXX Q-VoiceTM
system clock
* System clock: 4MHz~8MHz (2.4V) * RC oscillator for system clock * Eight I/O pins * 2K14-bit program ROM * 808-bit RAM * Two 8-bit programmable timer counter and one time
* HALT function and wake-up feature reduce power
consumption
* PWM circuit direct drive speaker or output by
transistor
* 32-pin DIP package
base counter
Applications
* Intelligent educational leisure products * Alert and warning systems * Sound effect generators
General Description
The HT83XXX series are 8-bit high performance microcontroller with voice synthesizer and tone generator. The HT83XXX is designed for applications on multiple I/Os with sound effects, such as voice and melody. It can provide various sampling rates and beats, tone levels, tempos for speech synthesizer and melody generator. Low voltage detection is provided to reset under 2.2V or 3.3V. The HT83XXX is excellent for versatile voice and sound effect product applications. The efficient MCU instructions allow users to program the powerful custom applications. The system frequency of HT83XXX can be up to 8MHz under 2.4V and include a HALT function to reduce power consumption.
Selection Table
Body Voice ROM size Voice length HT83003 64K-bit 3 sec HT83006 128K-bit 6 sec HT83009 192K-bit 9 sec HT83018 384K-bit 18 sec HT83036 768K-bit 36 sec HT83048 1024K-bit 48 sec HT83072 1536K-bit 72 sec
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Preliminary
Block Diagram
STACK0 STACK1 P ro g ra m ROM P ro g ra m C o u n te r STACK2 STACK3 IN T C In te rru p t C ir c u it
HT83XXX
TM R0 TM R0C
S Y S C L K /4
8 - b it
In s tr u c tio n R e g is te r
MP0 M
U X
DATA M e m o ry
TM R1 TM R1C
S Y S C L K /4
8 - b it
In s tr u c tio n D ecoder ALU T im in g G e n e r a tio n
MUX
T im e B a s e
S Y S C L K /1 0 2 4
S Y S C L K /4
STATUS PAC PA
S h ifte r PORT A PA0~PA7
OS RE VD VS S
D
S
C1
ACC H ALT E N /D IS
W DTS M 256 W D T P r e s c a le r
U X
W DTRC OSC S Y S C L K /4
L V D /L V R
L a tc h C o u n te r In te rfa c e PW M SYS CLK 8 -s ta g e P r e s c a le r
SYS CLK PW M1 PW M2
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Preliminary
Pin Assignment
NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NC NC NC NC NC NC NC NC NC PA0 PA1 PA2 PA3 PA4 PA5 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 NC NC NC NC NC NC PW M2 PW M1 VCCA1 VCC GND GNDA1 OSC1 RES PA7 PA6
HT83XXX
H T 8 3 0 0 3 /H T 8 3 0 0 6 /H T 8 3 0 0 9 /H T 8 3 0 1 8 H T 8 3 0 3 6 /H T 8 3 0 4 8 /H T 8 3 0 7 2 3 2 D IP -A
Pad Assignment
HT83003/HT83006/HT83009
(0 ,0 ) 16 15 14 1 PA0 2 3 4 PA3 PA2 PA1 5 PA4 6 PA5 7 8 PA7 PA6 9 RES 10 OSC1 11 12 13 PW M2 PW M1 VCCA1
GNDA1
GND
VCC
Chip size: 2220 1355 (mm)2 * The IC substrate should be connected to VSS in the PCB layout artwork.
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Preliminary
HT83018/HT83036
HT83XXX
(0 ,0 )
16 15 14 1 2 3 4 5 6 7 8 9 10 11 12 13 VCC GND GNDA1
PW M2 PW M1 VCCA1
* The IC substrate should be connected to VSS in the PCB layout artwork. HT83048/HT83072
* The IC substrate should be connected to VSS in the PCB layout artwork.
PA1 PA0
PA3 PA2
PA5 PA4
Chip size: 2220 1660 (mm)2
PA7 PA6
OSC1 RES
(0 ,0 )
16 15 14 1 2 3 4 5 6 7 8 9 OSC1 11 12 13 VCC GND GNDA1
PW M2 PW M1 VCCA1
RES PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
Chip size: 2220 2335 (mm)2
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Preliminary
Pad Coordinates
HT83003/HT83006/HT83009 Pad No. 1 2 3 4 5 6 7 8 HT83018/HT83036 Pad No. 1 2 3 4 5 6 7 8 HT83048/HT83072 Pad No. 1 2 3 4 5 6 7 8 X -982.145 -876.845 -766.245 -666.245 -555.645 -455.645 -345.045 -245.045 Y -998.050 -998.050 -998.050 -998.050 -998.050 -998.050 -998.050 -998.050 Pad No. 9 10 11 12 13 14 15 16 X -135.205 -31.229 758.645 858.645 958.645 841.895 841.895 841.895 X -982.145 -876.845 -766.245 -666.245 -555.645 -455.645 -345.045 -245.045 Y -660.550 -660.550 -660.550 -660.550 -660.550 -660.550 -660.550 -660.550 Pad No. 9 10 11 12 13 14 15 16 X -135.205 -31.229 758.645 858.645 958.645 841.895 841.895 841.895 X -982.145 -876.845 -766.245 -666.245 -555.645 -455.645 -345.045 -245.045 Y -508.050 -508.050 -508.050 -508.050 -508.050 -508.050 -508.050 -508.050 Pad No. 9 10 11 12 13 14 15 16 X -135.205 -31.229 758.645 858.645 958.645 841.895 841.895 841.895
HT83XXX
Y -508.050 -508.050 -490.400 -490.400 -490.400 -345.550 -224.050 -85.450
Y -660.550 -660.550 -642.900 -642.900 -642.900 -498.050 -376.550 -237.950
Y -998.050 -998.050 -980.400 -980.400 -980.400 -835.550 -714.050 -575.450
Pin Description
Pad Name PA0~PA7 GND VDD GNDA1 VDDA1 RES OSC1 PWM1, PWM2 I/O I/O 3/4 3/4 3/4 3/4 I 3/4 O Mask Option Wake-up, Pull-high or None 3/4 3/4 3/4 3/4 3/4 RC 3/4 Description Bidirectional 8-bit I/O port. Each bit can be configured as a wake-up input by mask option. Software instructions determine the CMOS output or Schmitt trigger input with or without pull-high resistor (mask option). Negative power supply, ground Positive power supply PWM negative power supply, ground PWM positive power supply, ground Schmitt trigger reset input, active low OSC1 is connected to an RC network for the internal system clock. PWM output for driving a external transistor or speaker
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Preliminary
Absolute Maximum Ratings
Supply Voltage ..........................VSS+2.4V to VSS+5.2V Input Voltage .............................VSS-0.3V to VDD+0.3V
HT83XXX
Storage Temperature ...........................-50C to 125C Operating Temperature ..........................-20C to 70C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol VDD ISTB IDD IOL IOH IO IO VIL1 VIH1 fSYS Parameter Operating Voltage Standby Current Operating Current I/O Port Sink Current I/O Port Source Current PWM Source Current PWM Source Current Input Low Voltage (RES) Input High Voltage (RES) System Frequency Test Conditions VDD 3/4 3V 3V 3V 3V 3V 3V 3V 3V 3V Conditions 3/4 No load, system HALT No load, fSYS=4MHz VOL=0.3V VOH=2.7V VOL=0.3V VOH=2.7V 3/4 3/4 ROSC=100kW ROSC=62kW Min. 2.4 3/4 3/4 17 -12 121 -81 3/4 3/4 3.7 7.4 Typ. 3/4 1 1.2 3/4 3/4 3/4 3/4 1.5 2.2 4.0 8.0 Max. 5.2 3/4 1.5 3/4 3/4 3/4 3/4 3/4 3/4 4.5 MHz 8.6 Unit V mA mA mA mA mA mA V V
A.C. Characteristics
Symbol fSYS fTIMER tWDTOSC tWDT tRES tSST Parameter System Clock (RC OSC) Timer Input Frequency Watchdog Oscillator Watchdog Time-out Period (RC) External Reset Low Pulse Width System Start-up Timer Period Test Conditions VDD 3V 3V 3V 3V 3/4 3/4 Conditions 3/4 3/4 3/4 Without WDT prescaler 3/4 Power-up or wake-up from HALT Min. 4 0 45 12 1 3/4 Typ. 3/4 3/4 90 23 3/4 1024 Max. 8 8 180 45 3/4 3/4 Unit MHz MHz ms ms ms tSYS
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Preliminary
Functional Description
Execution Flow The system clock for the HT83XXX series is derived from either a crystal or an RC oscillator. It is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to effectively execute within one cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. Program Counter - PC The 13-bit program counter (PC) controls the sequence in which the instructions stored in program ROM are executed. After accessing a program memory word to fetch an instruction code, the contents of the program counter are
T1 T2 T3 T4 T1 T2
HT83XXX
incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt or return from subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instruction. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. The lower byte of the program counter (PCL) is a read/write register (06H). Moving data into the PCL performs a short jump. The destination must be within 256 locations. When a control transfer takes place, an additional dummy cycle is required.
T3 T4 T1 T2 T3 T4
S y s te m
C lo c k PC
PC
PC+1
PC+2
. e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )
. e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
. e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
Execution flow
Mode Initial Reset Time Base Overflow Timer Counter 0 Overflow Timer Counter 1 Overflow Skip Loading PCL Jump, Call Branch Return from Subroutine
Program Counter *12 0 0 0 0 *11 0 0 0 0 *10 0 0 0 0 *9 0 0 0 0 *8 0 0 0 0 *7 0 0 0 0 *6 0 0 0 0 PC+2 *12 #12 S12 *11 #11 S11 *10 #10 S10 *9 #9 S9 *8 #8 S8 @7 #7 S7 @6 #6 S6 @5 #5 S5 @4 #4 S4 @3 #3 S3 @2 #2 S2 @1 #1 S1 @0 #0 S0 *5 0 0 0 0 *4 0 0 0 0 *3 0 0 1 1 *2 0 1 0 1 *1 0 0 0 0 *0 0 0 0 0
Program counter Note: *12~*0: Program counter bits #12~#0: Instruction code bits S12~S0: Stack register bits @7~@0: PCL bits
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Program Memory - ROM The program memory stores the program instructions that are to be executed. It also includes data, table and interrupt entries, addressed by the program counter along with the table pointer. The program memory size for HT83XXX is 204814 bits. Certain locations in the program memory are reserved for special usage:
* Location 000H
HT83XXX
Table Location Any location in the ROM space can be used as look up tables. The instructions TABRDC [m] (used for any bank) and TABRDL [m] (only used for last page of program ROM) transfer the contents of the lower-order byte to the specified data memory [m], and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined. The higher-order bytes of the table word are transferred to the TBLH. The table higher-order byte register (TBLH) is read only. The table pointer (TBLP) is a read/write register, which indicates the table location. Stack Register - Stack The stack register is a special part of the memory used to save the contents of the program counter (PC). This stack is organized into four levels. It is neither part of the data nor part of the program space, and cannot be read or written to. Its activated level is indexed by a stack pointer (SP) and cannot be read or written to. At a subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack. The program counter is restored to its previous value from the stack at the end of subroutine or interrupt routine, which is signaled by return instruction (RET or RETI). After a chip resets, SP will point to the top of the stack. The interrupt request flag will be recorded but the acknowledgment will be inhibited when the stack is full and a non-masked interrupt takes place. After the stack pointer is decremented (by RET or RETI), the interrupt request will be serviced. This feature prevents stack overflow and allows programmers to use the structure more easily. In a similar case, if the stack is full and a CALL is subsequently executed, stack overflow occurs and the first entry is lost.
This area is reserved for program initialization. The program always begins execution at location 000H each time the system is reset.
* Location 004H
This area is reserved for the time base interrupt service program. If the ETBI (intc.1) is activated, and the interrupt is enabled and the stack is not full, the program will jump to location 004H and begins execution.
* Location 008H
This area is reserved for the 8-bit timer counter 0 interrupt service program. If a timer interrupt results from a timer counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program will jump to location 008H and begins execution.
* Location 00CH
This area is reserved for the 8-bit timer counter 1 interrupt service program. If a timer interrupt results from a timer counter 1 overflow, and if the interrupt is enabled and the stack is not full, the program will jump to location 00CH and begins execution.
0000H 0004H 0008H 000CH 0015H In itia l A d d r e s s T im e B a s e In te r r u p t S u b r o u tin e T im e r 0 In te r r u p t S u b r o u tin e T im e r 1 In te r r u p t S u b r o u tin e P ro g ra m ROM
07..H
Program memory
Instruction TABRDC [m] TABRDL [m]
Table Location *10 0 1 *9 0 1 *8 0 1 *7 @7 @7 *6 @6 @6 *5 @5 @5 *4 @4 @4 *3 @3 @3 *2 @2 @2 *1 @1 @1 *0 @0 @0
Table location Note: *10~*0: Current program ROM table @7~@0: Write @7~@0 to TBLP pointer register
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Data Memory - RAM The data memory is designed with 808 bits. The data memory is further divided into two functional groups, namely, special function registers (00H~2AH) and general purpose user data memory (30H~7FH). Although most of them can be read or be written to, some are read only. The special function registers include an indirect addressing register (R0:00H), memory pointer register (MP0:01H), accumulator (ACC:05H), program counter lower-order byte register (PCL:06H), table pointer (TBLP:07H), table higher-order byte register (TBLH:08H), status register (STATUS:0AH), interrupt control register 0 (INTC:0BH), timer counter 0 (TMR0:0DH), timer counter 0 control register (TMR0C:0EH), timer counter 1 (TMR1L:10H), timer counter 1 control register (TMR1C:11H), I/O registers (PA:12H), I/O control registers (PAC:13H), voice ROM address latch0[21:0] (LATCH0H:18H, LATCH0M:19H, LATCH0L:1AH), time base control bit EBTI (INTC.1), PWM control register (PWMCR:26H), PWM output (PWMD:28H), voice ROM latch data register (LATCHD:2AH). The general purpose data memory, addressed from 30H~7FH, is used for data and control information under instruction commands. The areas in the RAM can directly handle the arithmetic, logic, increment, decrement and rotate operations. Except some dedicated bits, each bit in the RAM can be set and reset by SET [m].i and CLR [m].i. They are also indirectly accessible through the Memory Pointer register 0 (MP0:01H).
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0.H 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1.H
20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH LATCHD PW MD PW MCR R0
HT83XXX
MP0
ACC PCL TBLP TBLH W DTS STATUS IN T C TM R0 TM R0C TM R1 TM R1C PA PAC
LATCH 0H LATCH 0M LATCH 0L
S p e c ia l P u r p o s e DATA M EM ORY
:U nused.
R e a d a s "0 "
2.H 30H G e n e ra l P u rp o s e D a ta M e m o ry 7.H
RAM mapping Address RAM Mapping 00H 01H 05H 06H 07H 08H 09H R0 MP0 ACC PCL TBLP TBLH WDTS Read/Write R/W R/W R/W R/W R/W R R/W Description Indirect addressing register 0 Memory pointer 0 Accumulator Program counter lower-order byte address Table pointer lower-order byte register Table higher-order byte content register Watchdog Timer option setting register
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Address RAM Mapping 0AH 0BH 0DH 0EH 10H 11H 12H 13H 18H 19H 1AH 26H 28H 2AH STATUS INTC TMR0 TMR0C TMR1 TMR1C PA PAC LATCH0H LATCH0M LATCH0L PWMCR PWMD LATCHD Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R Status register Interrupt control register 0 Timer counter 0 register Timer counter 0 control register Timer counter 1 register Timer counter 1 control register Port A I/O data register Port A I/O control register Voice ROM address latch 0 [A21~A16] Voice ROM address latch 0 [A15~A8] Voice ROM address latch 0 [A7~A0] PWM control register PWM output data D7~D0 Voice ROM data register Description
HT83XXX
2BH~2FH Unused 30H~7FH User data RAM Note: R: Read only W: Write only R/W: Read/Write R/W User data RAM
Indirect Addressing Register Location 00H is indirect addressing registers that are not physically implemented. Any read/write operation of [00H] accesses the RAM pointed to by MP0 (01H) respectively. Reading location 00H indirectly returns the result 00H. While, writing it indirectly leads to no operation. Accumulator - ACC (05H) The accumulator (ACC) is related to the ALU operations. It is also mapped to location 05H of the RAM and is capable of operating with immediate data. The data movement between two data memory locations must pass through the ACC. Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic operations and provides the following functions:
* Arithmetic operations (ADD, ADC, SUB, SBC, DAA) * Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ etc)
Status Register - STATUS (0AH) This 8-bit STATUS register (0AH) consists of a zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PD), watchdog time-out flag (TO). It also records the status information and controls the operation sequence. Except the TO and PD flags, bits in the status register can be altered by instructions similar to other registers. Data written into the status register does not alter the TO or PD flags. Operations related to the status register, however, may yield different results from those intended. The TO and PD flags can only be changed by a Watchdog Timer overflow, chip power-up, or clearing the Watchdog Timer and executing the HALT instruction. The Z, OV, AC, and C flags reflect the status of the latest operations. On entering the interrupt sequence or executing the subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status is important, and if the subroutine is likely to corrupt the status register, the programmer should take precautions and save it properly.
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Labels C Bits 0 Function
HT83XXX
C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PD is cleared by system power-up or executing the CLR WDT instruction. PD is set by executing the HALT instruction. TO is cleared by system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 Status register
AC Z OV PD TO 3/4
1 2 3 4 5 6, 7
Interrupts The HT83XXX provides two 8-bit programmable timer interrupts, and a time base interrupt. The Interrupt Control registers (INTC:0BH) contain the interrupt control bits to set to enable/disable and the interrupt request flags. Once an interrupt subroutine is serviced, all other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may happen during this interval but only the interrupt request flag is recorded. If a certain interrupt needs servicing within the service routine, the EMI bit and the corresponding INTC bit may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from becoming full. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack and then branching to subroutines at the specified location(s) in the program memory. Only the program counter is pushed onto the stack. The programmer must save the contents of the register or status register (STATUS) in advance if they are altered by an interrupt service program which corrupts the desired control sequence. The Internal Timer Counter 0 Interrupt is initialized by setting the timer counter 0 interrupt request flag (T0F:bit 5 of INTC), caused by a timer counter 0 overflow. When the interrupt is enabled, and the stack is not full and the T0F bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (T0F) will be reset and the EMI bit cleared to disable further interrupts. The Internal Timer Counter 1 Interrupt is initialized by setting the timer counter 1 interrupt request flag (T1F:bit 6 of INTC), caused by a timer counter 1 overflow. When the interrupt is enabled, and the stack is not full and the Rev. 0.00 11
T1F bit is set, a subroutine call to location 0CH will occur. The related interrupt request flag (T1F) will be reset and the EMI bit cleared to disable further interrupts. Time Base Interrupt is triggered by set INTC.1 (ETBI) which sets the related interrupt request flag (TBF:bit 4 of INTC). When the interrupt is enabled, and the stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (TBF) and EMI bits will be cleared to disable other interrupts. During the execution of an interrupt subroutine, other interrupt acknowledgment are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (of course, if the stack is not full). To return from the interrupt subroutine, the RET or RETI instruction may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Interrupts occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests, the following table shows the priority that is applied. These can be masked by resetting the EMI bit. The timer counter 0/1 interrupt request flag (T0F/T1F) which enables timer counter 0/1 control bit (ET0I/ET1I), the time base interrupt request flag (TBF) which enables time base control bit (ETTBI) from the interrupt control register (INTC:0BH) EMI, ETBI, ET0I, ET1I are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt begin serviced. Once the interrupt request flags (T0F, T1F, TBF) are set, they will remain in the INTC register until the interrupts are serviced or cleared by a software instruction. It is recommended that application programs do not use CALL subroutines within an interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only February 19, 2003
Preliminary
HT83XXX
one stack is left and the interrupt enable is not well controlled, once a CALL subroutine if used in the interrupt subroutine will corrupt the original control sequence. Register Bit No. 0 1 2 INTC (0BH) 3 4 5 6 7 Label EMI ETBI ET0I ET1I TBF T0F T1F 3/4 Function Controls the master (global) interrupt (1= enabled; 0= disabled) Controls the time base interrupt (1= enabled; 0= disabled) Controls the timer 0 interrupt (1= enabled; 0= disabled) Controls the timer 1 interrupt (1= enabled; 0= disabled) Time base interrupt request flag (1= active; 0= inactive) Timer 0 request flag (1= active; 0= inactive) Timer 1 request flag (1= active; 0= inactive) Unused bit, read as 0 INTC0 register Interrupt Source Time Base Interrupt Timer Counter 0 Overflow Timer Counter 1 Overflow Priority 1 2 3 Vector 04H 08H 0CH
Oscillator Configuration The HT83XXX provides RC oscillator circuit for the system clock. The signal is used for the system clock. The HALT mode stops the system oscillator to conserve power. If the RC oscillator is used, an external resistor between OSC1 and VSS is required, and the range of the resistance should be from 62kW to 100kW. The system clock, divided by 4. The RC oscillator provides the most cost effective solution. However, the frequency of the oscillation may vary with VDD, temperature, and the chip itself due to process variations. It is therefore not suitable for timing sensitive operations where accurate oscillator frequency is desired.
OSC1
Watchdog Timer - WDT The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator) or instruction clock (system clock divided by 4), decided by mask options. This timer is designed to prevent a software malfunction or sequence jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by mask option. If the Watchdog Timer is disabled, all the executions related to the WDT result in no operation. Once the internal WDT oscillator (RC oscillator with period 78ms normally) is selected, it is first divided by 256 (8-stages) to get the nominal time-out period of approximately 20ms. This time-out period may vary with temperature, VDD and process variations. By invoking the WDT prescaler, longer time-out period can be realized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of WDTS(09H)) can give different time-out period. If WS2, WS1, WS0 all equal to 1, the division ratio is up to 1:128, and the maximum time-out period is 2.6 seconds. If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock.
RC
O s c illa to r
System oscillator
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S y s te m C lo c k /4 M ask O p tio n S e le c t W D T P r e s c a le r 8 - b it C o u n te r 7 - b it C o u n te r
HT83XXX
W DT OSC
8 -to -1 M U X W D T T im e - o u t
W S0~W S2
Watchdog Timer
The WDT overflow under normal operation will initialize a chip reset and set the status bit TO. Whereas in the HALT mode, the overflow will initialize a warm re set only the PC and SP are reset to zero. To clear the contents of the WDT (including the WDT prescaler), WS7 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 WS6 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 WS5 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 WS4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 WS3 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
three methods are adopted; external reset (external reset (a low level to RES), software instructions, or a HALT instruction. The software instruction is CLR WDT and execution of the CLR WDT instruction will clear the WDT. WS2 0 0 0 0 1 1 1 1 WS1 0 0 1 1 0 0 1 1 WS0 0 1 0 1 0 1 0 1 Division Ratio 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128
WDTS register
Power Down - HALT The HALT mode is initialized by a HALT instruction and results in the following:
* The system oscillator will be turned off but the WDT
oscillator keeps running (if the WDT oscillator is selected).
* The contents of the on chip RAM and registers remain
unchanged.
* WDT and WDT prescaler will be cleared and recount
again.
* All I/O ports maintain their original status. * The PD flag is set and the TO flag is cleared.
The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake up the device by mask option. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If awakening from an interrupt, two sequence may occur. If the related interrupt is disabled or the interrupt is enabled by the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes place. Once a wake-up event occurs, it takes 1024 system clock period to resume normal operation. In other words, a dummy cycle period will be inserted after a wake-up. If the wake-up results from an interrupt acknowledge, the actual interrupt subroutine will be delayed by one more cycle. If the wake-up results in next instruction execution, this will be executed immediately after a dummy period is finished. If an interrupt request flag is set to 1 before entering the HALT mode, the wake-up function of the related interrupt will be disabled. To minimize power consumption, all I/O pins should be carefully managed before entering the HALT status.
The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset causes a device initialization and the WDT overflow performs a warm reset. By examining the TO and PD flags, the reason for the chip reset can be determined. The PD flag is cleared when the system powers-up or executes the CLR WDT instruction, and is set when the HALT instruction is executed. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the PC and SP. The other maintain their original status. Rev. 0.00 13
February 19, 2003
Preliminary
Reset There are 3 ways in which a reset can occur:
* RES reset during normal operation * RES reset during HALT * WDT time-out reset during normal operation
RES SST 1 0 -s ta g e R ip p le C o u n te r P o w e r - o n D e te c tin g HALT W DT W DT T im e - o u t R eset
HT83XXX
W a rm R eset
The WDT time-out during HALT is different from other chip reset conditions, since it can perform a warm re set that resets only the PC and SP, leaving the other circuits in their original state. Some registers remain unchanged during any other reset conditions. Most registers are reset to their initial condition when the reset conditions are met. By examining the PD flag and TO flag, the program can distinguish between different chip resets. TO 0 u 0 1 1 PD 0 u 1 u 1 RESET Conditions RES reset during power-up RES reset during normal operation RES wake-up HALT WDT time-out during normal operation WDT wake-up HALT
OSCI
C o ld R ese
Reset configuration The functional unit chip reset status are shown below. PC Interrupt Prescaler WDT Timer counter Input/output ports SP Timer Counter 0/1 The TMR0/TMR1 is internal clock source only, i.e. (TM1, TM0)=(1,0). There is a 3-bit prescaler (TMRS2, TMRS1, TMRS0) which defines different division ratio of TMR0/TMR1s clock source. Label Bits Function 000H Disable Clear Clear. After master reset, WDT begins counting Off Input mode Points to the top of the stack
Note: u stands for unchanged To guarantee that the system oscillator has started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses after a system power up or when awakening from a HALT state. When a system power up occurs, the SST delay is added during the reset period. But when the reset comes from the RES pin, the SST delay is disabled. Any wake-up from HALT will enable the SST delay.
VDD RES S S T T im e - o u t C h ip R eset tS
ST
Reset timing chart
V
DD
Defines the operating clock source (TMRS2, TMRS1, TMRS0) 000: clock source/2 001: clock source/4 TMRS2, 010: clock source/8 TMRS1, 0~2 011: clock source/16 TMRS0 100: clock source/32 101: clock source/64 110: clock source/128 111: clock source/256 TE TON 3 4 5 6 7 Defines the TMR0/TMR1 active edge of timer counter Enable/disable timer counting (0=disabled; 1=enabled) Unused bit, read as 0 Defines the operating mode (TM1, TM0) TMR0C/TMR1C register
RES
3/4 TM0, TM1 Reset circuit Note:
TMR0C/TMR1C bit 3 always write 0 TMR0C/TMR1C bit 5 always write 0 TMR0C/TMR1C bit 6 always write 1 TMR0C/TMR1C bit 7 always write 0
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Preliminary
The TMR0C is the timer counter 0 control register, which defines the timer counter 0 options. The timer counter 1 has the same options as the timer counter 0 and is defined by TMR1C. To enable the counting operation, the Timer ON bit (TON; bit 4 of TMR0C/TMR1C) should be set to 1. The overflow of the timer counter is one of the wake-up sources. No matter what the operation mode is, writing a 0 to ET0I/ET1I can disable the corresponding interrupt service.
(T M R S 2 , T M R S 1 , T M R S 0 ) S y s te m C lo c k 8 -S ta g e P r e s c a le r TON O v e r flo w to In te rru p t T im e r C o u n te r 0 /1 P r e lo a d R e g is te r
HT83XXX
The TMR0/1 is internal clock source only. There is a 3-bit prescaler (TMRS2, TMRS1, TMRS0) which defines different division ratio of TMR0/1s clock source. Time Base The time base enables the counting operation by INTC.1 (ETBI) bit. The overflow to interrupt as set INTC.1. The time base is internal clock source only. Time base of 1ms to overflow as system clock is 4MHz. Time base of 0.5ms to overflow as system clock is 8MHz.
D a ta B u s R e lo a d
T im e r C o u n te r 0 /1
Timer counter 0/1
S y s te m C lo c k /4
1024
O v e r flo w to In te rru p t
Time base
The registers states are summarized in the following table. Register Reset (Power On) PC MP0 ACC TBLP TBLH WDTS STATUS INTC TMR0 TMR0C TMR1 TMR1C LATCH0H LATCH0M LATCH0L PA PAC PWMCR PWMD LATCHD Note: 0000H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0111 --00 xxxx -000 0000 xxxx xxxx 00-0 1--xxxx xxxx 00-0 1------ --xx xxxx xxxx xxxx xxxx 1111 1111 1111 1111 -00- 00-0 xxxx xxxx xxxx xxxx WDT Time-out RES Reset (Normal Operation) (Normal Operation) 0000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0111 --1u uuuu -000 0000 uuuu uuuu 00-0 1--uuuu uuuu 00-0 1------ --uu uuuu uuuu uuuu uuuu 1111 1111 1111 1111 -uu- uu-u uuuu uuuu uuuu uuuu 0000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0111 --uu uuuu -000 0000 uuuu uuuu 00-0 1--uuuu uuuu 00-0 1------ --uu uuuu uuuu uuuu uuuu 1111 1111 1111 1111 -uu- uu-u uuuu uuuu uuuu uuuu RES Reset (HALT) 0000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0111 --01 uuuu -000 0000 uuuu uuuu 00-0 1--uuuu uuuu 00-0 1------ --uu uuuu uuuu uuuu uuuu 1111 1111 1111 1111 -uu- uu-u uuuu uuuu uuuu uuuu WDT Time-out (HALT) 0000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --11 uuuu -uuu uuuu uuuu uuuu uu-u u--uuuu uuuu uu-u u------ --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uu- uu-u uuuu uuuu uuuu uuuu
u means unchanged; x means unknown; - means undefined
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Preliminary
Low Voltage Reset - LVR The microcontroller provides low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device is within 2.2V or 3.3V (by mask option), such as changing a battery, the LVR will automatically reset the device internally. Input/Output Ports There are 8 bidirectional input/output lines in the microcontroller, labeled from PA, which are mapped to the data memory of [12H] respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A, [m] (m=12H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC) to control the input/output configuration. With this control register, CMOS output or Schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically under software control. To function as an input, the corresponding latch of the control register must write 1. The input source also depends on the control register. If the control register bit is 1, the input will
HT83XXX
read the pad state. If the control register bit is 0, the contents of the latches will move to the internal bus. The latter is possible in the read-modify-write instruction. For output function, CMOS is the only configuration. These control registers are mapped to locations 13H. After a chip reset, these input/output lines remain at high levels or floating state (dependent on pull-high options). Each bit of these input/output latches can be set or cleared by SET [m].i and CLR [m].i (m=12H) instructions. Some instructions first input data and then follow the output operations. For example, SET [m].i, CLR [m].i, CPL [m], CPLA [m] read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability of waking-up the device. The wake-up capability of port A is determined by mask option. There is a pull-high option available for all I/O lines. Once the pull-high option is selected, all I/O lines have pull-high resistors. Otherwise, the pull-high resistors are absent. It should be noted that a non-pull-high I/O line operating in input mode will cause a floating state.
D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r D W r ite I/O
D CK S
Q
V V
DD
Q
DD
W eak P u ll- u p M a s k O p tio n
Q CK S
PA0~PA7 PB0~PB7 PC 0~PC 7
Q
M U X
R e a d I/O S y s te m W a k e - U p ( P A o n ly ) M a s k O p tio n
Input/output ports
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Preliminary
Audio Output - PWMD (28H)
HT83XXX
The HT83XXX provides one 8-bit PWM interface for driving an external 8W speaker. The programmer must write the voice data to register PWMD (28H) Pulse Width Modulation Control Register - PWMCR (26H) Bit 7 3/4 Bit 6 (R/W) P1 Bit 5 (R/W) P0 Bit 4 3/4 Bit 3 (R/W) Single_PWM Bit 2 (R/W) VROMC Bit 1 3/4 Bit 0 (R/W) PWMC
PWMC: Start bit of PWM output
* PWM start counter: 0 to 1 * PWM stop counter: 1 to 0
PWM2 and the PWM1 will get a GND level voltage after setting start bit to 1. PWM output Initial low level , and stop in low level If PWMC from low to high then start PWM output and 5kHz/6kHz/8kHz latch new data , if no update then keep the old value. If PWMC from high to low, in duty end, stop PWM output and stop the counter. Voice ROM Data Address Latch Counter The voice ROM data address latch counter is the handshaking between the microcontroller and voice ROM, where the voice codes are stored. One 8-bit of voice ROM data will be addressed by setting 21-bit address latch counter LATCH0H/LATCH0M/LATCH0L. After the 8-bit voice ROM data is addressed, a few instruction cycles (4ms at least) will be generated to latch the voice ROM data, then the microcontroller can read the voice data from LATCHD (2AH). Example: Read an 8-bit voice ROM data which is located at address 000007H by address latch 0 set mov mov mov mov mov mov call mov [26H].2 A, 07H A, 00H A, 00H Delay Time A, LATCHD ; Enable voice ROM circuit ; ; ; ; Delay a short period of time ; Get voice data at 000007H
After waiting one cycle end , stop the PWM counter and keep in low signal VROMC: Enable voice ROM power circuit (1=enable; 0=disable) Single_PWM: Driving PWM signal only by PWM1 port. (1=enable; 0=disable) The HT83xxx provides an 8-bit (bit 7 is a sign bit, if Single_PWM = 0) PWM interface. The PWM provides two pad outputs: PWM1, PWM2 which can directly drive a piezo or a 8W speaker without adding any external element (green mode), or using only port PWM1 (Set Single_PWM = 1) to drive piezo or a 8W speaker with external element. When Setting Single_PWM = 1, choose voice data7~data1 as the output data (no sign bit on it). Setting data to P0 and P1 can generate various sampling rates (5kHz/6kHz/8kHz): P1 P0 0 0 1 0 1 0 Sampling Carrier Preload PWM Code Rate frequency Times Range 5kHz 6kHz 8kHz X 30kHz 30kHz 32kHz X 6 5 4 X 0~127 0~127 0~124 X
LATCH0L, A ; Set LATCH0L to 07H LATCH0M, A ; Set LATCH0M to 00H LATCH0H, A ; Set LATCH0H to 00H
3/43/4
If the sign bit is 0, then the signal is output to PWM1and the PWM2 will get a GND level voltage after setting start bit to 1. If the sign bit is 1, then the signal is output to
D a ta B u s
S y s te m
c lo c k
P r e s c a le r .0 .1
P W M D a ta B u ffe r (2 8 H )
B it7 ( s ig n b it) V
DD
S ta r t b it 2 6 H .0 PW MI .2
D iv .
CK PE
7 B its C o u n te r ( B it6 ~ B it0 ) O v e r flo w
D CK Q
Q
R
P W M D A C 1 fo r S P E A K E R
P W M D A C 2 fo r S P E A K E R
PWM Rev. 0.00 17 February 19, 2003
Preliminary
Mask Option Mask Option PA Wake-up Watchdog Timer (WDT) Description Enable or disable PA wake-up function Enable or disable WDT function One or two CLR instruction WDT clock source is from WDTOSC or T1 Enable or disable low voltage reset Low voltage reset at 2.2V or 3.3V Enable or disable PA pull-high
HT83XXX
Low Voltage Reset (LVR) PA Pull-high fOSC - ROSC Table (VDD=5V) fOSC 4MHz10% 6MHz10% 8MHz10%
ROSC 100kW 75kW 62kW
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Preliminary
Application Circuits
V
DD
HT83XXX
VDD OSC1 R (1 0 0 k W ~ 6 2 k W ) V VCCA1 RES 0 .1 m . C PA0~PA7 PW M1 PW M2 S peaker (8 /1 6 ) 47m. GNDA1
DD
GND
H T83XXX
Single PWM Mode
V
DD
VDD OSC1 R V VCCA1 RES 0 .1 m . C PA0~PA7 PW M1 PW M2 47m. GNDA1 V
DD DD
(1 0 0 k W ~ 6 2 k W )
S peaker (8 /1 6 ) Q2 NPN BCE
GND
H T83XXX
Note: * For normal application, a capacitor C is not necessary. However, if you want to extend the reset time , a 0.1mF capacitor can be placed on the RES pin.
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February 19, 2003
Preliminary
Package Information
32-pin DIP (600mil) Outline Dimensions
A 32 B 1 16 17
HT83XXX
H C D E . G
a
I
Symbol A B C D E F G H I a
Dimensions in mil Min. 1635 535 145 125 16 50 3/4 595 635 0 Nom. 3/4 3/4 3/4 3/4 3/4 3/4 100 3/4 3/4 3/4 Max. 1665 555 155 145 20 70 3/4 615 670 15
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February 19, 2003
HT83XXX
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Sales Office) 11F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Semiconductor (Shanghai) Inc. 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor (Hong Kong) Ltd. Block A, 3/F, Tin On Industrial Building, 777-779 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Holmate Semiconductor, Inc. 46712 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright O 2003 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
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February 19, 2003

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